The present disclosure relates generally to integrated circuits (ICs), which may include programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs). More particularly, the present disclosure relates to generating enhanced circuit designs to implement on PLDs.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Integrated circuits (ICs) take a variety of forms. For instance, programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs) are ICs that may be highly flexible devices. FPGAs include logic that may be programmed after manufacturing to provide functionality that the FPGA may be designed to support. Thus, FPGAs may contain programmable logic, or combinational logic blocks, that may perform a variety of functions on the FPGAs, according to a circuit design of a user. Some applications for the FPGAs, such as error detection and correction circuits, cryptography circuits, and the like, use large, amorphous systems of combinational logic blocks (e.g., XOR, OR, NAND, AND, etc.). The amorphous systems may refer to circuit diagrams that describe logical implementations of large, complex interconnected networks of combinational logic blocks. In one example, an amorphous system may include tangles of numerous intertwined or partially overlapping XOR gates. As may be appreciated, the numerous combinational logic blocks may be arranged and/or organized in millions or billions of candidate physical implementations that enable implementing the amorphous system of combinational logic blocks. In some instances, the physical implementations vary from the logical implementations of the amorphous systems (e.g., an XOR gate with a large number of inputs in the logical implementation may be broken down into multiple XOR gates in the physical implementations).
The physical implementation that is selected to implement the amorphous system may be loaded onto an integrated circuit. As may be appreciated, there may be numerous physical constraints that may affect the choice of the physical implementation of the amorphous system. For example, the integrated circuit may include a set number of logic array blocks (LABs) that are interconnected via logic array block buses. The logic array blocks may each contain one or more adaptive logic modules (ALMs) interconnected via adaptive logic module buses. To implement the physical implementation of the amorphous system, the combinational logic blocks may be converted into the adaptive logic modules, which are grouped in a certain number (e.g., ten) to the logic array blocks. It may be desirable to reduce the number of logic array blocks used by a physical implementation of an amorphous system of combinational logic blocks to enable cost-savings and maintaining contiguous free space of programmable circuitry. However, as may be appreciated, it may be very difficult to find a physical implementation of the amorphous system of combinational logic blocks that can be implemented efficiently on a relatively small number of logic array blocks.